Transmeta

Founded in 1995, Transmeta began as a stealth start-up. The company was largely successful in hiding its ambitions until its official company launch on January 19, 2000.^[17] Over 2000 non-disclosure agreements (NDAs) were signed during the stealth period.^[18] Throughout Transmeta's first few years, little was known about exactly what it would be offering. Its web site went online in mid 1997 and for approximately two and a half years displayed nothing but the text, "This web page is not yet here."

On November 12, 1999, a cryptic comment in the HTML appeared:^[19]

Yes, there is a secret message, and this is it: Transmeta's policy has been to remain silent about its plans until it had something to demonstrate to the world. On January 19, 2000, Transmeta is going to announce and demonstrate what Crusoe processors can do. Simultaneously, all of the details will go up on this Web site for everyone on the Internet to see. Crusoe will be cool hardware and software for mobile applications. Crusoe will be unconventional, which is why we wanted to let you know in advance to come look at the entire Web site in January, so that you can get the full story and have access to all of the real details as soon as they are available.

Transmeta attempted to staff the company in secret although speculation online was not uncommon.^[20] Information gradually came out of the company suggesting it was working on a very long instruction word (VLIW) design that translated x86 code into its own native VLIW code.

On January 19, 2000, Transmeta held a launch event at Villa Montalvo in Saratoga, California^[21] and announced to the world that it had been working on an x86 compatible dynamic binary translation processor named Crusoe. It also released an 18-page whitepaper^[3] describing the technology.

Transmeta marketed their microprocessor technology as extraordinarily innovative and revolutionary in the low-power market segment. They had hoped to be both power and performance leaders in the x86 space but initial reviews of Crusoe indicated the performance fell significantly short of projections.^[22] Also, while Crusoe was in development, Intel and AMD significantly ramped up speeds and began to address concerns about power consumption. So Crusoe was rapidly cornered into a low-volume, small form factor (SFF), low-power segment of the market.

On November 7, 2000 (US election day), Transmeta had their initial public offering at the price of $21 a share. The value reached a high of $50.26 before settling down to $46 a share on opening day. This made Transmeta the last of the great high tech IPOs of the dot-com bubble. Their opening day performance would not be surpassed until Google’s IPO in 2004.

The company had its first layoffs in July 2002, reducing the headcount of the company by 40%.^[23]

On October 14, 2003, Transmeta announced the Efficeon processor which was claimed to have twice the performance of the original Crusoe CPU at the same frequency. However, performance was still weak relative to the competition and the complexity of the chip had increased significantly. The greater size and power consumption may have diluted a key market advantage Transmeta's chips had previously enjoyed over the competition.

In January 2005, the company announced its first strategic restructuring away from being a semiconductor product company and began to focus on licensing intellectual property.^[8] In March 2005, Transmeta announced that it was laying off 68 people while retaining 208 employees. Sony was reported to be a key licensee of Transmeta technology and approximately half of the remaining employees were to work on LongRun2 power optimization technology for Sony.

El 31 de mayo de 2005, Transmeta anunció la firma de acuerdos de compra de activos y licencias con Culture.com Technology Limited de Hong Kong. El acuerdo fracasó debido a retrasos en la obtención de licencias de exportación de tecnología del Departamento de Comercio de Estados Unidos , y las partes anunciaron la rescisión de los acuerdos el 9 de febrero de 2006.

El 10 de agosto de 2005, Transmeta anunció su primer trimestre rentable. Posteriormente, el 20 de marzo de 2006, GameSpot informó que Transmeta estaba trabajando en un proyecto de Microsoft sin nombre . Resultó ser una plataforma segura bajo la marca AMD para el programa FlexGo de Microsoft . ^{[ 24 ]}

El 11 de octubre de 2006, Transmeta anunció que había presentado una demanda contra Intel Corporation por infracción de diez patentes estadounidenses de Transmeta relacionadas con arquitectura informática y tecnologías de eficiencia energética. La demanda alegaba que Intel había infringido y seguía infringiendo las patentes de Transmeta mediante la fabricación y venta de diversos microprocesadores, entre ellos, como mínimo, las líneas de productos Pentium III, Pentium 4, Pentium M, Core y Core 2 de Intel.

El 7 de febrero de 2007, Transmeta cerró su división de servicios de ingeniería, despidiendo a 75 empleados. Esto coincidió con el anuncio de que la empresa dejaría de desarrollar y vender hardware y se centraría en el desarrollo y la concesión de licencias de propiedad intelectual. ^{[ 9 ]} Posteriormente, AMD invirtió 7,5 millones de dólares en Transmeta, con la intención de utilizar la cartera de patentes de la empresa en tecnologías de eficiencia energética. ^{[ 25 ]}

El 24 de octubre de 2007, Transmeta anunció un acuerdo para resolver su demanda contra Intel Corporation. Intel acordó pagar $150 millones por adelantado y $20 millones por año durante cinco años a Transmeta, además de retirar sus contrademandas contra Transmeta. Transmeta también acordó licenciar varias de sus patentes y ceder una pequeña cartera de patentes a Intel como parte del acuerdo. ^{[ 12 ]} Transmeta también acordó no volver a fabricar procesadores compatibles con x86. Un punto importante de controversia en el litigio con Intel fue el pago de aproximadamente $34 millones a tres ejecutivos de Transmeta. ^{[ 26 ] [ 27 ]} A finales de 2008, Intel y Transmeta llegaron a un nuevo acuerdo para transferir los $20 millones por año en una suma global.

El 8 de agosto de 2008, Transmeta anunció que había licenciado sus tecnologías de chips LongRun y ​​de bajo consumo a Nvidia por una tarifa de licencia única de 25 millones de dólares. ^{[ 13 ]} El 17 de noviembre, Transmeta anunció la firma de un acuerdo definitivo para ser adquirida por Novafora , una empresa de procesadores de vídeo digital con sede en Santa Clara, California , por 255,6 millones de dólares en efectivo, sujeto a ajustes en función del capital circulante. ^{[ 28 ]} El acuerdo se finalizó el 28 de enero de 2009, cuando Novafora anunció la finalización de su adquisición de Transmeta. ^{[ 29 ]}

Intellectual Venture Funding LLC ^{[ 30 ]} completó la adquisición de la cartera de patentes anteriormente desarrollada y propiedad de Transmeta Corporation el 4 de febrero de 2009. ^{[ 28 ]}

Debido a problemas financieros e incapacidad para ejecutar, Novafora quebró a finales de julio de 2009. ^{[ 31 ] [ 32 ]}

Transmeta tuvo una sucesión de 6 directores ejecutivos diferentes que dirigieron la empresa a lo largo de su historia.

Entre su equipo de tecnólogos, Transmeta empleó a algunas de las figuras más públicas de la industria, incluyendo al fundador de Linux, Linus Torvalds , al desarrollador del kernel de Linux, Hans Peter Anvin , al autor de Yacc , Stephen C. Johnson , ^{[ 33 ] [ 34 ]} y al desarrollador de juegos Dave D. Taylor . En parte debido a la presencia de estas figuras, la industria estaba constantemente llena de rumores y " teorías de la conspiración ", lo que resultó en excelentes relaciones con la prensa .

Transmeta recibió un total de 969 millones de dólares en financiación a lo largo de su existencia.

Crusoe fue la primera familia de microprocesadores de Transmeta, nombrada en honor al personaje literario Robinson Crusoe . ^{[ 7 ]}

Transmeta perdió mucha credibilidad y sufrió críticas significativas debido a las grandes discrepancias entre el rendimiento y el consumo de energía proyectados y los resultados reales. Aunque el consumo de energía fue algo mejor que las ofertas de Intel y AMD, la experiencia del usuario final (es decir, la duración de la batería) solo mostró una mejora general marginal. ^{[ 37 ]} En primer lugar, el software de transformación de código (CMS) combinado con la arquitectura de caché infló artificialmente las comparaciones entre los benchmarks y las aplicaciones del mundo real. Esto se debe a la naturaleza repetitiva de los benchmarks y su pequeño tamaño. La sobrecarga del software CMS puede haber sido una causa clave del rendimiento mucho menor para muchas aplicaciones del mundo real; la arquitectura de núcleo VLIW simple no podía competir en aplicaciones computacionalmente intensivas; y la interfaz del puente sur estaba limitada por su bajo ancho de banda para gráficos u otras aplicaciones intensivas de E/S. Algunos benchmarks estándar incluso no se ejecutaron, lo que puso en duda la afirmación de compatibilidad total con x86. ^{[ 22 ]}

El procesador Efficeon fue el diseño de procesador VLIW de 256 bits de segunda generación de Transmeta . Al igual que el Crusoe (una arquitectura VLIW de 128 bits ), Efficeon priorizaba la eficiencia computacional, el bajo consumo de energía y una baja generación de calor.

Un Transmeta Efficeon de 1,6 GHz modelo 2004 (fabricado con un proceso de 90 nm ) tenía aproximadamente el mismo rendimiento y características de consumo de energía que un Intel Atom de 1,6 GHz de 2008 (fabricado con un proceso de 45 nm ). ^{[ 38 ]} El Efficeon incluía un puente norte integrado , mientras que el Atom, su competidor, requería un chip de puente norte externo, lo que reducía gran parte de las ventajas del Atom en cuanto al consumo de energía.

El procesador Transmeta Efficeon solucionó muchas de las deficiencias del Crusoe y mostró una mejora real de aproximadamente el doble. Su chip era considerablemente más pequeño que el Pentium 4 y el Pentium M, al compararlos con la misma tecnología de proceso. El chip del Efficeon, fabricado a 90 nm, tiene un ^{tamaño de}  68  mm² , lo que representa el 60 % del Pentium 4 a 90 nm (112 mm² ⁾ , y ambos procesadores cuentan con una caché L2 de 1 MB.  

The notion of selling a product into a specific thermal envelope was typically not understood by the mass of reviewers, who tended to compare Efficeon to the gamut of x86 microprocessors, regardless of power consumption or application. One such example of this criticism suggests the performance still significantly lagged behind Intel's Pentium M (Banias) and AMD's Mobile Athlon XP.^[39]

Code Morphing Software (CMS) is the technology used by Transmeta microprocessors to execute x86 instructions.^[42][43] In broad view, CMS reads x86 instructions and generates instructions for a proprietary VLIW processor, in the style of Shade.^[44] CMS translation is much more expensive than Shade's, but produces much higher quality code. CMS also contains an interpreter and simulates both user-mode and system mode operation.

Code Morphing Software consisted of an interpreter, a runtime system and a dynamic binary translator. x86 instructions were first interpreted one instruction at a time and profiled, then depending upon the frequency of execution and other heuristics, CMS would progressively generate more optimized translations.^[3][4][5]

Similar technologies existed in the 1990s: Wabi for Solaris and Linux, FX!32 for Alpha and IA-32 EL for Itanium, open-source DAISY,^[45] the Mac 68K emulator for the PowerPC. The Transmeta approach set a much higher bar for x86 compatibility due to its ability to execute all x86 instructions from initial boot up to the latest multimedia instructions.

The operation of Transmeta's code morphing software is similar to the final optimization pass of a conventional compiler. Considering a fragment of 32-bit x86 code:

add eax,dword ptr [esp] // load data from stack, add to eax add ebx,dword ptr [esp] // ditto, for ebx mov esi,[ebp] // load esi from memory sub ecx,5 // subtract 5 from ecx register

This is first converted simplistically into native instructions:

ld %r30,[%esp] // load from stack, into temporary add.c %eax,%eax,%r30 // add to %eax, set condition codes. ld %r31,[%esp] add.c %ebx,%ebx,%r31 ld %esi,[%ebp] sub.c %ecx,%ecx,5

The optimizer then eliminates common sub-expressions and unnecessary condition code operations and, potentially, applies other optimizations such as loop unrolling:

ld %r30,[%esp] // load from stack only once add %eax,%eax,%r30 add %ebx,%ebx,%r30 // reuse data loaded earlier ld %esi,[%ebp] sub.c %ecx,%ecx,5 // only this last condition code needed

Finally, the optimizer groups individual instructions ("atoms") into long instruction words ("molecules") for the underlying hardware:

ld %r30,[%esp]; sub.c %ecx,%ecx,5 ld %esi,[%ebp]; add %eax,%eax,%r30; add %ebx,%ebx,%r30

These two VLIW molecules could potentially execute in fewer cycles than the original instructions could on an x86 processor.^[3]

Transmeta claimed several technical benefits to this approach:

1. As the market leaders Intel and/or AMD would extend the core x86 instruction set, Transmeta could quickly upgrade their product with a software upgrade rather than requiring a respin of their hardware.
2. Performance and power can be tuned in software to meet market needs.
3. It would be relatively simple to fix hardware design or manufacturing flaws in the hardware using software workarounds.
4. More time could be spent concentrating on enhancing the capabilities of the core or reducing its power consumption without worrying about 33 years of backward compatibility to the x86 architecture.
5. The processor could emulate multiple other architectures, possibly even at the same time. (At its initial Crusoe launch, Transmeta demonstrated pico-Java and x86 running intermixed on the native hardware.)

Prior to Crusoe's release, rumors indicated Transmeta was relying on these benefits to develop a hybrid PowerPC and x86 processor. But Transmeta would initially concentrate solely on the extremely low-power x86 market.

The ability to quickly update products without a hardware respin was demonstrated in 2002 with an in-the-field upgrade (a download) to enhance CPU performance of the Crusoe based HP Compaq TC1000 tablet PC. It was used again in 2004 when NX bit and SSE3 support were added to the Transmeta Efficeon product line without requiring hardware changes. In the field upgrades were rare in practice due to system hardware vendors not wanting to incur additional customer support costs or spend additional money on QA for the potential upgrades or bug fixes to shipped products they had already closed the revenue books on.

In conjunction with its code-morphing software the Efficeon most closely mirrors the feature set of IntelPentium 4 processors, although, like AMDOpteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode. NX bit support is available starting with CMS version 6.0.4.

Efficeon's computational performance relative to mobile CPUs like the IntelPentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.

Efficeon came in two package types: a 783- and a 592-contact ball grid array. Its power consumption was moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it could be passively cooled.

Two generations of this chip were produced. The first generation (TM8600) was manufactured using a TSMC 130 nm process and produced at speeds up to 1.1 GHz. The second generation (TM8800 and TM8820) was manufactured using a Fujitsu 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.

Internally, the Efficeon had two arithmetic logic units, two load/store/add units, two execute units, two floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. The VLIW core could execute a 256-bit VLIW instruction per cycle. A VLIW is called a molecule and has room to store eight 32-bit instructions (called atoms) per cycle.

The Efficeon had a 128-KB L1 instruction cache, a 64-KB L1 data cache and a 1-MB L2 cache. All caches were on die.

Additionally, Efficeon code morphing software (CMS) reserved a small portion of main memory (typically 32 MB) for its cache of dynamically translated x86 instructions.

In principle, it should be possible to optimize x86 code to favor Code Morphing Software, or even for compilers to target the native VLIW architecture directly. However, writing in 2003, Linus Torvalds (who used to be employed in Transmeta) apparently dismissed these approaches as unrealistic:^[46][47]

The native crusoe code – even if it was documented and available – is not very conducive to general-purpose OS stuff. It has no notion of memory protection, and there's no MMU for code accesses, so things like kernel modules simply wouldn't work.

The translations are usually better than statically compiled native code (because the whole CPU is designed for speculation, and the static compilers don't know how to do that), and thus going to native mode is not necessarily a performance improvement.

So no, it wouldn't really benefit from it, not to mention that it's not even an option since Transmeta has never released enough details to do it anyway. Largely for simple security concerns – if you start giving interfaces for mucking around with the "microcode", you could do some really nasty things.

[...I meant...] "you cannot do that". And we won't even tell the details of how you cannot do that.

In fact, even inside transmeta you cannot do that, without having a specially blessed version of the flash that allows upgrades. If you ever see a machine with a prominent notice saying "CMS upgraded to development version", then that's a hint that it's a machine that TMTA developers could change.

Subsequent reverse engineering, published in 2004, clarifies some details of the native VLIW architecture and associated instruction set, and suggests that there are fundamental limitations that preclude porting an operating system such as Linux to it.^[48][49]

The same work also compares Transmeta's patented technology with prior art published and in some cases patented by IBM, and suggests that some claims might not stand detailed scrutiny.^[49]